EDA for IC Implementation, Circuit Design, and Process Technology provides a convenient, comprehensive reference focused on the back-end aspects of EDA.
Features:
- Presents thorough coverage of the back-end aspects of EDA for implementation, physical design, and manufacturability
- Focuses on the major areas involved in physical design, including process simulation, device modeling, and layout extraction
- Provides a general introduction to each topic as well as a survey of state-of-the-art tools and methods
- Features contributions from top experts in their respective areas from leading industrial and academic institutions around the world
Contents
RTL to GDS-II, or Synthesis, Place, and Route
Design Flows
- Invention
- Implementation
- Integration
- Future Scaling Challenges
Logic Synthesis
- Behavioral and Register Transfer-Level Synthesis
- Two-Level Minimization
- Multilevel Logic Minimization
- Enabling Technologies for Logic Synthesis
- Sequential Optimization
- Physical Synthesis
- Multivalued Logic Synthesis
Power Analysis and Optimization from Circuit to Register-Transfer Levels
- Power Analysis
- Circuit-Level Power Optimization
- Logic Synthesis for Low Power
Equivalence Checking
- Equivalence Checking Problem
- Boolean Reasoning
- Combinational Equivalence Checking
- Sequential Equivalence Checking
Digital Layout - Placement
- Global Placement
- Detailed Placement and Legalizers
- Placement Trends
- Academic and Industrial Placers
Static Timing Analysis
- Representation of Combinational and Sequential Circuits
- Gate Delay Models
- Timing Analysis for Combinational Circuits
- Timing Analysis for Sequential Circuits
- Clocking Disciplines: Edge-Triggered Circuits
- Clocking and Clock-Skew Optimization
- Statistical Static Timing Analysis
Structured Digital Design
- Datapaths
- Programmable Logic Arrays
- Memory and Register Files
- Structured Chip Design
Routing
- Types of Routers
- A Brief History of Routing
- Common Routing Algorithms
- Additional Router Considerations
Exploring Challenges of Libraries for Electronic Design
- What Does It Mean to Design Libraries
- How Did We Get Here, Anyway?
- Commercial Efforts
- What Makes the Effort Easier?
- The Enemies of Progress
- Environments That Drive Progress
- Libraries and What They Contain
Design Closure
- Current Practice
- The Future of Design Closure
Tools for Chip-Package Codesign
- Drivers for Chip-Package Codesign
- Digital System Codesign Issues
- Mixed-Signal Codesign Issues
- I/O Buffer Interface Standard and Other Macromodels
Design Databases
- Modern Database Examples
- Fundamental Features
- Advanced Features
- Technology Data
- Library Data and Structures: Design-Data Management
- Interoperability
FPGA Synthesis and Physical Design
- System-Level Tools
- Logic Synthesis
- Physical Design
- Looking Forward
Analog and Mixed-Signal Design
Simulation of Analog and RF Circuits and Systems
- Differential-Algebraic Equations for Circuits via Modified Nodal Analysis
- Device Methods
- Basic Circuit Simulation: DC Analysis
- Steady-State Analysis
- Multitime Analysis
- Noise in RF Design
Simulation and Modeling for Analog and Mixed-Signal Integrated Circuits
- Top-Down Mixed-Signal Design Methodology
- Mixed-Signal and Behavioral Simulation
- Analog Behavioral and Power Model Generation Techniques
- Symbolic Analysis of Analog Circuits
Layout Tools for Analog Integrated Circuits and Mixed-Signal Systems-on-Chip: A Survey
- Analog Layout Problems and Approaches
- Analog Cell Layout Strategies
- Mixed-Signal System Layout
- Field-Programmable Analog Arrays
Physical Verification
Design Rule Checking
- Geometric Algorithms for Physical Verification
- Hierarchical Data Structures
- Time Complexity of Hierarchical Analysis
- Connectivity Models
- Parallel Computing
- Future Roles for Verification
Resolution Enhancement Techniques and Mask Data Preparation
- Lithographic Effects
- RET for Smaller k1
- Software Implementations of RET Solutions
- Mask Data Preparation
Design for Manufacturability in the Nanometer Era
- Taxonomy of Yield Loss Mechanisms
- Logic Design for Manufacturing
- Parametric Design for Manufacturing Methodologies
- Design for Manufacturing Integration in the Design Flow: Yield-Aware Physical Synthesis
Design and Analysis of Power Supply Networks
- Voltage-Drop Analysis Modes
- Linear System Solution Techniques
- Models for Power Distribution Networks
Noise Considerations in Digital ICs
- Why Has Noise Become a Problem for Digital Chips?
- Noise Effects in Digital Designs
- Static Noise Analysis
- Electrical Analysis
- Fixing Noise Problems
Layout Extraction
- Early History
- Problem Analysis
- System Capabilities
- Converting Drawn Geometrics to Actual Geometrics
- Designed Device Extraction
- Connectivity Extraction
- Parasitic Resistance Extraction
- Capacitance Extraction Techniques
- Inductance Extraction Techniques
- Network Reduction
- Process Variation
Mixed-Signal Noise Coupling in System-on-Chip Design: Modeling, Analysis, and Validation
- Mechanisms and Effects of Mixed-Signal Noise Coupling
- Modeling of Mixed-Signal Noise Coupling
- Mixed-Signal Noise Measurement and Validation
- Application to Placement and Power Distribution Synthesis
Technology CAD
Process Simulation
- Process Simulation Methods
- Ion Implantation
- Diffusion
- Oxidation
- Etch and Deposition
- Lithography and Photoresist Modeling
- Silicidation
- Mechanics Modeling
- Putting It All Together
Device Modeling - From Physics to Electrical Parameter Extraction
- MOS Technology and Intrinsic Device Modeling
- Parasitic Junction and Inhomogeneous Substrate Effects
- Device Technology Alternative
High-Accuracy Parasitic Extraction
- Extraction via Fast Integral Equation Methods
- Statistical Capacitance Extraction
Index
See also:
Electronic Design Automation for Integrated Circuits Handbook 2-Volume Set
to see books • videos • cd-roms of related interest