Engineering book from C.H.I.P.S.

EDA for IC System Design, Verification, and Testing
Volume 1

by Louis Scheffer

EDA for IC System Design, Verification, and Testing explains in detail system-level design, micro-architectural design, verification tools, and test methods.


  • Presents thorough coverage of the front-end aspects of EDA for IC design, verification, and testing
  • Focuses on the major areas involved in logic design , including system-level and micro-architectural design
  • Provides a general introduction to each topic as well as a survey of state-of-the-art tools and methods
  • Features contributions from top experts in their respective areas from leading industrial and academic institutions around the world.




  • Introduction to Electronic Design Automation for Integrated Circuits
  • System Level Design
  • Micro-Architecture Design
  • Logical Verification
  • Test
  • RTL to GDS-II, or Synthesis, Place, and Route
  • Analog and Mixed-Signal Design
  • Physical Verification
  • Technology Computer-Aided Design

The Integrated Circuit Design Process and Electronic Design Automation

  • Verification
  • Implementation
  • Design for Manufacturing

System Level Design

Tools and Methodologies for System-Level Design

  • Characteristics of Video Applications
  • Other Application Domains
  • Platform Characteristics
  • Models of Computation and Tools for Model-Based Design
  • Simulation
  • Hardware/Software Cosynthesis

System-Level Specification and Modeling Languages

  • A Survey of Domain-Specific Languages and Methods
  • Heterogeneous Platforms and Methodologies

SoC Block-Based Design and IP Assembly

  • The Economics of Reusable IP and Block-Based Design
  • Standard Bus Interfaces
  • Use of Assertion-Based Verification
  • Use of IP Configurators and Generators
  • The Design Assembly and Verification Challenge
  • The SPIRIT XML Databook Initiative

Performance Evaluation Methods for Multiprocessor System-on-Chip Design

  • Overview of Performance Evaluation in the Context of System Design Flow
  • MPSoC Performance Evaluation

System-Level Power Management

  • Dynamic Power Management
  • Battery-Aware Dynamic Power Management
  • Software-Level Dynamic Power Management

Processor Modeling and Design Tools

  • Processor Modeling Using ADLs
  • ADL-Driven Methodologies

Embedded Software Modeling and Design

  • Synchronous vs. Asynchronous Models
  • Synchronous Models
  • Asynchronous Models
  • Research on Models for Embedded Software

Using Performance Metrics to Select Microprocessor cores for IC Designs

  • The ISS as Benchmarking Platform
  • Ideal Versus Practical Processor Benchmarks
  • Standard Benchmark Types
  • Prehistoric Performance Ratings: MIPS, MOPS, and MFLOPS
  • Classic Processor Benchmarks (The Stone Age)
  • Modern Processor Performance Benchmarks
  • Configurable Processors and the Future of Processor-Core Benchmarks

Parallelizing High-Level Synthesis: A Code Transformational Approach to High-Level Synthesis

  • Background and Survey of the State of the Art
  • Parallelizing HLS
  • The SPARK PHLS Framework

Micro-Architecture Design

Cycle-Accurate System-Level Modeling and Peformance Evaluation

  • System Modeling and Design Methodology
  • Back-Annotation of System-Level Modeling Objects
  • Automatic Extraction of Statistical Features
  • Open System-Level Modeling Issues

Micro-Architectural Power Estimation and Optimization

  • Background
  • Architectural Template
  • Micro-Arcitectural Power Modeling and Estimation
  • Micro-Architectural Power Optimization

Design Planning

  • Floorplans
  • Wireplans
  • A Formal System For Trade-Offs

Logical Verification

Design and Verification Languages

  • Design Languages
  • Verification Languages

Digital Simulation

  • Event-vs. Process-Oriented Simulation
  • Logic Simulation Methods and Algorithms
  • Impact of Languages on Logic Simulation
  • Logic Simulation Techniques
  • Impact of HVLs on Simulation

Using Transactional-Level Models in an SoC Design Flow

  • Related Work
  • Overview of the System-to-RTL Design Flow
  • TLM - A Complementary View for the Design Flow
  • TLM Modeling Application Programming Interface
  • Example of a Multimedia Platform
  • Design Flow Automation

Assertion-Based Verification

  • State of the Art

Hardware Acceleration and Emulation

  • Emulator Architecture Overview
  • Design Modeling
  • Debugging
  • Use Models
  • The Value of In-Circuit Emulation
  • Considerations for Successful Emulation

Formal Property Verification

  • Formal Property Verification Methods and Technologies
  • Software Formal Verification



  • The Objectives of Design-For-Test for Microelectronics Products
  • Overview of Chip-Level Design-For-Test Techniques

Automatic Test Pattern Generation

  • Combinational ATPG
  • Sequential ATPG
  • ATPG and SAT
  • Applications of ATPG
  • High-Level ATPG

Analog and Mixed Signal Test

  • Analog Circuits and Analog Specifications
  • Testability Analysis
  • Fault Modeling and Test Specification
  • Catastrophic Fault Modeling and Simulation
  • Parametric Faults, Worst-Case Tolerance Analysis, and Test Generation
  • Design for Test - An Overview
  • Oscillation-Based DFT/BIST
  • PLL, VCO, and Jitter Testing
  • Review of Jitter Measurement Techniques


See also:
Electronic Design Automation for Integrated Circuits Handbook 2-Volume Set

click here to see books videos cd-roms of related interest


EDA for IC System Design, Verification, and Testing Volume 1:
by Louis Scheffer
2006 $108.95 + shipping

EDA for IC Implementation, Circuit Design, and Process Technology Volume 2:
by Louis Scheffer
2006 $108.95 + shipping
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